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CPU Rockchip RK3576
Ƶ ĺCortex-A72@2.3GHz+ĺCortex-A53@2.2Ghz
ҵ4G+32G 4GBڴ(Ӳ32GB)32GB EMMC洢
ҵ4G+32G 4GBڴ(Ӳ32GB)32GB EMMC洢
ԴоƬ ʹRK806_S
GPU ARM Mali-G52 MC3,OpenGL ES1.1/2.0/3.2, Vulkan 1.1, OpenCL 2.0
NPU ֧6T ֧INT4/INT8/INT16/FP16/BF16/TF32
ý  
Ӳ룺H.264H.265,4K@60fps
Ӳ룺H.264H.265VP9AV1AVS28K@30fps4K@120fps
 
ʾ  
ֶ֧
֧һHDMI/eDP TXýӿ
֧һMIPI DSI-2 TXӿ
֧һ·USB/DPϽӿ
 

İ

ߴ 6.5*5.0cm
߶ 1.5mm
ͺ 80pin AXK5F80347YG AXK6F80347YG 0.5mm
-20浽+60
С11.5V12.4V׼12V
չ Ŷ320ûչ

İӿԴ

MIPI CSI 5  
֧ 5 CSI-2 ӿ
4 ӿΪ 2 D-PHY v1.2 data-lane2.4Gbps/lane
4 ӿڿϳ 2 ӵ 4 data-lane ӿ
1 ӿ֧ 4 D-PHY data-lane 3 C-PHY trios
D-PHY v2.0lane speed is 4.5Gbps
C-PHY v1.1trio speed is 2.4Gsps
 
DVP 1  
8/10/12/16-bit ׼DVPӿڣ150MHz룻
֧ BT.601/BT.656 BT.1120 VI ӿڣ
 
HDMI/eDP TX 1  
֧1 HDMI / eDP TX Ͻӿ
HDMI ӿ
HDMI v2.1
֧ 4K@120Hz
֧ݸʽRGB/YUV444/YUV422/YUV420 8/10-bit
֧ CECARC
HDCP v2.3 HDCP v1.4
eDPӿ
eDP v1.3
Main link containing 4 physical lanes
֧ 4K@60Hz
HDCP v1.3
 
DP TX 1  
֧1 · USB / DP Ͻӿ
USB ӿ
USB 3.2 Gen1x1
Dual-Role Device(DRD)
DisplayPort TX ӿ
DisplayPort v1.4
Supports 1/2/4 lanes with lane speed including 1.622.75.4 and 8.1Gbps
֧ 4K@120Hz
֧ݸʽRGB/YUV444/YUV422/YUV420 8/10-bit
֧ Multi-Stream Transport (MST) with 3 displays
֧ DP Altmode on USB Type-C
֧ HDCP v2.3 and HDCP v1.3
 
MIPI DSI 1  
֧ 1 MIPI DSI-2 TX ӿ
D-PHY v2.0 or C-PHY v1.1
4 data lanes on D-PHY
3 data trios on C-PHY
֧ 2560 x 1600@60Hz
֧ݸʽRGB (up to 10bit)
 
Parallel 1  
֧ 1 ӿ
֧ RGB/BT.656/BT1120
֧ 1920 x 1080@60Hz
֧ݸʽRGB (up to 10bit)
 
EBC 1  
֧ 1 EBC ӿ
֧ E-ink EPD (Electronic paper Display)
֧ 2560 x 1920 Ӳ
֧߿ȣ16-bit
ָ֧ߴ 32 level gray scale
֧ Direct modeLUT mode3-window mode
֧ window display mode
 
SAI 5  
֧ 5 SAI ӿ
SAI 0/1 ֧ 4 TX lanes 4 RX lanes
SAI 2/3/4 ֧ 1TX lane 1 RX lane
֧ I2S/TDM/PCM ģʽ *2
֧߲ʣ192KHz
֧Ƶֱʣ16bits 32bits
 
SPDIF TX 2 ֧ 2 · SPDIF TX ˿
SPDIF RX 2 ֧ 2 · SPDIF RX ˿
PDM 2  
8 channelsƵֱʴ16 ~24 λʴ192KHz
֧PDMģʽ
 
Ethernet 2  
2·GMACṩRGMII / RMIIӿ
֧10/100/1000Mbpsݴ
 
Combo high speed interface interface 2  
֧ 1 PCIe2.1/SATA3.1 interface with one data lane
֧ 1 PCIe2.1/SATA3.1/USB3.2 Gen1x1 interface with one data lane
 
USB 2.0 OTG 2 ֧·USB2.0 OTG
SDIO 2 SDIO v3.04-bit data bus widths
SPI 5  
֧ two chip-select in each interface
֧ serial-master serial-slave mode
 
I2C 9  
֧7λ10λַģʽ
׼ģʽݴ100k bits/sڿģʽ400k bits/s
 
I3C 2 ֧ 2 I3C master ports
UART 12  
2·64 bit FIFOɷֱTXRX
֧5λ6λ7λ8λշʸߴ4Mbps
12·UART֧Զģʽ
12·UART֧RS485ģʽ
 
CAN 2  
ѭ CAN CAN FD 淶
֧CAN׼֡չ֡շ
֧8192-bit receive FIFO
 
DSMC 1  
Supports up to select 4 chips
Supports 8-wire and 16-wire serial transfer mode
Supports configurable serial address width:16 bits or 32 bits
 
FlexBus 1  
Supports built-in DMA and ping-pong operation for allocating two address
Supports transmission and receiving mode
Supports single mode and continuous mode
 
PWM 16 ֧16ƬPWMлжϵIJֲ֧ģʽ
ADC 8 ֧8·12bitSAR-ADCʸߴ1MS/s
GPIO n  
е GPIO Աж
ֵ֧ƽͱشж
֧õƽ
֧ش½ش˫شж
֧
֧
 




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